Compiling for Special Architectures
13.0 Introduction
Early computers of the 1940's and 50's had small instruction sets which executed on a small number of also small (often 8-bit) registers. Hardware was expensive, and compiler techniques were just developing. Floating-point operations, often implemented in software, were slow.
The 1960's and 70's saw a decrease in the price of hardware and the introduction of designs which modeled high-level language constructs such as loop instructions and array indexing. Many of these constructs were implemented in microcode; for this reason machine instructions were themselves translated to lower-level sequences of (micro-)code. These machines, when compared with reduced instruction set computers (RlSC's), are called ClSC's-Complex Instruction Set Computers.
Much of the information in this chapter applies equally well to CISC machines. Separation of the RISC discussion from parallel architecture issues is also somewhat artificial since RISC architectures may also be parallel architectures. We have avoid discussing specific machines and processors and discuss only their features.
One strong point exists for compiling for special architectures. This is that the hardware chip design and (optimizing) compiler design have often proceeded hand in hand. Rarely today is the compiler designer faced with a hardware design for which no consideration of how it is to be used has been made.