13.1 Compiling for RISC Machines
Interactions between programmers and hardware designers resulted in the hardware implementation of high-level language constructs. This led to large instruction sets and the proliferation of addressing modes. Research into the use of these complex instructions and addressing modes began to show that a small number of instructions and modes were used most frequently. For example, three of the DEC VAXTM's ten addressing modes account for 85% of the use; ten of the over 200 instructions on the IBM 370TM accounted for 67% of use [Muchnick, 1990].
Reduced Instruction Set Computers (RISC) are designed to reflect this simplicity. The return to smaller instruction sets and simpler addressing modes is not a return to the past, however. Random access memory is faster and cheaper. Registers and buses remain larger (generally 32 bits). Hardware design and implementation as well as compiler techniques are much better understood.
Nevertheless, RISC machines pose interesting problems for compiler designers, particularly in the areas of optimization and code generation. Because there are a larger number of registers, more program quantities can be kept in registers. Source level debugging of this highly optimized code has become a challenge.