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CS4515
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CS525F-2003
CS4515
-2003
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Spring 2004 - C-term
CS4515
- Computer Architecture & Organization
Fernando C. Colon
Osorio
Schedule:
M, T, R, F 10:00 - 10:55 AM, SL104
Textbook:
Computer
Organization & Design, Second Edition
by David A. Patterson & John L. Hennessy
Home
|Administrative Policies | Syllabus
| MySchedule
| # |
Week |
Subject |
Readings |
Due |
Assignments |
Class Notes |
Solutions |
| 01
02
|
January
12-16
|
Introduction
The Design Process
|
Chapter 1
|
Pset01
|
Technology Trends & RISC vs. CISC
Generations
|
CS4515-01.ppt,
pdf
CS4515-02.ppt,
pdf
|
|
| 03
04
05
06
|
19-24
|
The Design Process - II
Performance & Cost
Performance & Cost - II
CS4515-Test-01
|
Chapter 2 pp 52-89
Chapter 3 pp 104-206
|
Pset02
Pset-03
Project-01
DAN9600-V2
|
Amdahl's Law
CPI Law
|
CS4515-02a.ppt,
pdf
CS4515-03.ppt ,
pdf
CS4515-04.ppt.
pdf
|
|
| 07
08
09
10
|
26 - 30
|
ISA - I
ISA - II
ISA - III
Processor Arithmetic - I
|
Chapter 4 pp.208-250
Chapter 4 pp 250-312
|
Pset-04 |
|
CS4515-05.ppt,
pdf
CS4515-06.ppt,
pdf
|
Solutions-to-Exam#01
|
| 11
12
13
14
|
February
02 - 06
|
Processor Arithmetic - II
Floating Point Numbers
Processor: Data Path
& Execute Unit - I
Processor: Data Path & Execute Unit -II
|
Chapter 5 pp.336-399
|
|
|
CS4515-11.ppt,
pdf
|
|
| 15
16
17
18
|
09 - 13
|
Processor: Data Path & Execute Unit -III
Processor: Fetch & Decode Units - I
Processor: Fetch & Decode Units - II
Processor: Fetch & Decode Units - III
(Pipelines)
|
Chapter 6
|
|
|
CS4515-14.ppt,
pdf
|
|
|
19
20
21
22
|
16 - 20
|
Processor: Fetch & Decode Units - IV
(Pipelines)
Processor: Fetch & Decode Units - V
(Pipelines Stalls, Flushing, Code SCHEDULING)
Processor: Pipelines - V
Processor: Fetch & Decode Units - VI (ScoreBoarding,
Tomasulo's Algorithm)
|
Chapter
6
|
|
|
CS4515-16.pdf
CS4515-17.pdf
CS4515-18.pdf
|
|
| 23
24
25
26
|
23 - 27
|
Memory Hierarchy: Easy
Way to Performance - I
Memory Hierarchy: Easy Way to Performance - II
Memory and I/O - I
Memory and I/O - II
|
Chapter 7,
pp. 540-579
Chapter 8, pp.636-694
|
|
|
CS4515-19.pdf
|
|
| 27
28
|
March
01 - 05
|
Memory and I/O - II
Multiprocessors
|
Chapter 9, pp. 712-727
Chapter 9, pp. 734-748
|
|
|
|
|
| ADR-01 |
|
Exam 1 - TBA,
5:00 - 8:00 PM |
|
|
|
|
|
| ADR-02 |
|
Final |
|
|
|
|
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Computer Science Department,
Worcester Polytechnic Institute,
100 Institute Road, Worcester, MA 01609-2280, USA.
(508) 831-5357
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fcco@cs.wpi.edu
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