RISC Machine Features

Compiler Issues in RISC Machines

There is some controversy concerning what is or is not a RISC processor. The debate centers upon whether to classify a machine as RISC, as opposed to CISC, by architectural differences such as an abundance of registers or by performance measures such as performance of benchmark programs. In this section, we mention a number of architectural features commonly associated with RISC machines.

Small, Simpler Instruction Set and Few Addressing Modes

Small, simple and few are relative terms. Instruction set sizes are typically less than 150. Four or fewer addressing modes are common, although some processors have more.

Instruction set formats tend to be fixed in size, in contrast to variable length instruction formats of CISC machines. The number of these fixed-length formats is small, often on the order of two or three. This results in a faster (hard-wired) decoding.

Single-cycle operations allow the instructions to execute rapidly. Load-Store design dictates that only Load and Store instructions access memory. Ideally, these are the only instructions which take more than one machine cycle to execute.

Elimination of complex instructions eliminates the need for microcode.

Many Registers

Operations execute faster when the data is in a register. Thirty-two or more registers are common for RISC machines. Some have more. Hardware maintained sets of registers, called register windows, are organized in a circular queue, with a new set added to the tail of the queue and an older set removed from the head of the queue.

Levels of Memory

In addition to secondary memory, and a large number of registers, RISC processors include cache memory. Sometimes there is a separate cache memory for operations and operands. There may be separate buses to each cache.

Special-Purpose Architectures