Segmentation

Divide virtual space of the process into segments. Similar to paging except we can have segments match with needed sizes. See Fig 4-35, 4-37.

Address translation makes use of segment tables. A segment table contains an entry for each segment for a process. Entries contain:

Hardware Translation

The hardware performs the following address translation for every memory reference:

Sharing with Segmentation

Segmentation allows greater information sharing:

Process A: Process B:

Segment real length
number base  
0 200 150
1 400 120
2 600 80
Segment real length
number base  
0 350 44
1 0 150
2 400 120





status: B free A B A & B free A  
address: 0-149 150-199 200-349 350-399 400-519 520-599 600-679  

Physical memory layout:

Sample translations:
process virtual address physical address
B 123 $350 + 23 = 373 $
A 123 $400 + 23 = 423 $
B 223 $400 + 23 = 423 $

Note: Although Process A & B share the same segment, they are referenced through different virtual addresses!

A shared-segment table manages all shared segments. The table is only needed to (rapidly) determine which processes are sharing a segment.

Segment Faults

When a process references data in a missing segment, the hardware generates a segment fault that traps to the kernel. The fault handler:

The problem of which segment to remove when no free chunk exists is a general problem of caching. We will discuss it later.

Swapping a Segment to Backing Store

Because virtual address are bound to physical address at access time, swapped-out segments can be swapped back in at any physical location.

The size of a segment can vary dynamically as the process requests and returns memory.

Segmentation with Paging: MULTICS

Like multiple level page tables. Select the segment and then have a page table for each segment. Look at example Fig 4-39.

Segmentation with Paging: Intel Pentium

Intel Pentium supports segmentation. A segment selector is 16 bits (13 bits to identify a specific segment).

These bits map to a segment descriptor, which contains the base address and size of the segment. Combined with offset the result is a 32-bit linear address.

If paging is disabled this address is a physical address (pure segmentation).

If paging is enabled then address is a virtual address. Three level scheme:

  1. page directory entry--10 bits
  2. page table entry--10 bits
  3. offset--12 bits (4K page)

Note: can also disable segmentation by mapping entire address space to same segment and have pure paging. Then just use normal paging. Only OS/2 used segmentation feature.

Use protection rings (4 levels) for protection of data. Need a call gate to switch levels.