Homework 5
A Simulator for the LC-1: an LC-3 Assembly Language Program

Due on Tuesday, December 11, 2007 at 11:59 pm

Outcomes

• Write an LC-3 assembly language program that uses subroutines
• Write an LC-3 assembly language program that uses the stack
• Simulate a simple machine using an LC-3 assembly language program

Before Starting

Description of Problem

In this assignment, you will write a simulator for a machine called the LC-1, using LC-3 assembly language instructions.

The LC-1 ISA

The LC-1 ISA specifies eight instructions, described below. Three bits in the instruction, bits <15:13>, are used to represent the opcode. The remaining 13 bits, bits <12:0>, may be used to represent a 13-bit address.

The memory space being simulated contains 2^^13 locations, and the addressibility is 16 bits. The addressing mode is direct. (So, for example, if an instruction contains the bits 0 0000 0000 1100 in its address field, word 12 (decimal) of the program would be accessed.)

The LC-1 ISA has one condition register which is modified by three of the eight instructions: ADD, SUBTRACT, and LOAD. The condition register is set when a negative value is stored in the accumulator, otherwise, it is cleared.

LC-1 Instruction Set

• CALL

  opcode	bits <12:0>
  000	address13

  Description:  PC is pushed on the stack
                PC <- address13
  

• RETURN

  opcode	bits <12:0>
  001	0000000000000

  Description:  The stack is popped into PC
  

• ADD

  opcode	bits <12:0>
  010	address13

  Description:  Acc <- Acc + mem[address13]
  (The content of memory location address13 is added to the accumulator.
  The result is stored back in the accumulator.)
  

• BRANCH

  opcode	bits <12:0>
  011	address13

  Description:  If (n), PC <- address13
  (If the n condition bit is set, address13 is stored into the PC.)
  

• LOAD

  opcode	bits <12:0>
  100	address13

  Description:  Acc <- mem[address13]
  (The content of memory location address13 is loaded into the accumulator.)
  

• STORE

  opcode	bits <12:0>
  101	address13

  Description:  mem[address13] <- Acc
  (The accumulator is stored into memory location address13.)
  

• STOP

  opcode	bits <12:0>
  110	0000000000000

  Description:  Prints the message "Stopping the LC-1 simulator" to the console and stops execution
  

• SUBTRACT

  opcode	bits <12:0>
  111	address13

   
  Description:  Acc <- Acc - mem[address13]
  (The content of memory location address13 is subtracted from the accumulator.
  The result is stored back in the accumulator.)
   
  

Design Considerations

• The simulator you write in LC-3 assembly language should be placed starting at memory location x3000

• The PC for the LC-1 should be placed at memory location x3100. Each time the PC changes during the simulation of the LC-1 program, memory location x3100 should be updated to reflect this change.

• The accumulator for the LC-1 should be placed at memory location x3200. Each time the accumulator changes during the simulation of the LC-1 program, memory location x3200 should be updated to reflect this change.

• The condition register for the LC-1 should be placed at memory location x3300. Each time the condition register is set or reset during the simulation of the LC-1 program, memory location x3300 should be updated to reflect this change.

• The stack for the CALL and RETURN instructions should use memory locations x4000 - x4005 (maximum 5 locations for stack information). Initialize the stack pointer to x4005. You do not have to check for stack overflow or underflow.

• Since an address specified in LC-1 is 13 bits and an address specified in LC-3 is 16 bits, you can not simply use an LC-3 load/store instruction to simulate an LC-1 load/store instruction. To get around this problem, apply a simple workaround. Concatenate the 3-bit bit pattern, 011, to the 13 bits of the LC-1 address (the LC-1 machine code programs will be loaded into memory beginning at location x6000). For example, suppose you have the following LC-1 instruction,

  100 0 0001 0000 0010 ; Load from address 0 0001 0000 0010

  You can emulate this LC-1 instruction using the LC-3 LDR instruction. First, concatenate 011 to the address specified in the the LC-1 LOAD instruction. This produces the address

  0110 0001 0000 0010.

  Next, put this value into one of the LC-3 registers, for example, R2. The LC-3 instruction LDR R1, R2, #0 will perform the load, and the result will be stored into R1. Finally, R1 should be stored into the accumulator to complete the simulation of the LC-1 LOAD instruction.

• Algorithm - To begin writing your simulator, start with the code template shown below. The majority of the work is performed in the subroutine DECODE. The main loop of the simulator calls the FETCH and DECODE subroutines for each LC-1 instruction to simulate.

         .ORIG x3000
  ;=========================
  ; initialization block
  ;=========================
         ; ...
  
  ;=======================
  ; fetch the instruction
  ;=======================
  AGAIN JSR FETCH
  
  ;=======================
  ; decode the instruction
  ;=======================
        JSR DECODE
        BRnzp AGAIN
  
  ;===============================
  ; subroutine to perform fetch
  ;===============================
  FETCH ; ...
        ; ...
        RET
  
  ;===============================
  ; subroutine to perform decode
  ; and the rest of the
  ; instruction cycle
  ;===============================
  DECODE ; ...
         ; ...
         RET
         .END
  

  Once you can identify each opcode, tackle each of the LC-1 instructions one at a time. Test each LC-1 instruction with an appropriate test program before going on to the next instruction (we wrote some LC-1 test programs in class - you can use those test programs for some of your tests). You should load both the LC-1 program and the main simulator program into memory before running your simulation.

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