CS3013 Homework 3

Due date: Monday, October 6th

You must turn in your homework in written (or typed) form by the beginning of class on the date it is due.

The questions are based on material presented in class and reading material from the text.

Give brief answers to the following questions:

  1. Give two advantages to the use of multiple threads instead of the use of multiple processes.

  2. Consider an OS with the below process control block (PCB). Write another data structure that contains exactly enough information needed to support threads.

             struct PCB {
                 int     pid               /* Process ID */
                 int     state;            /* ready, running or blocked */
                 int     timeLeft;         /* time left since last time slide */
                 struct  SaveArea sa;      /* hardware state to save */
                 struct  InOut  *pIO;      /* pointer to IO descriptors */
                 struct  Heap   *pHeap;    /* pointer to heap */
                 struct  Stack  *pStack;   /* pointer to stack */

  3. Briefly explain the difference between internal and external fragmentation. In particular, explain why paging has no external fragmentation. What kind of fragmentation do you have with variable sized partitions?

  4. Given free, variable-sized memory partitions of 100K, 500K, 200K, 300K and 600K (stored in that order) and memory requests given chronologically in 250K, 419K, 205K and 330K. Assuming you allocate free memory using a first-fit (the first free partition big enough for the request is allocated) strategy, describe what requests go in what partiions. Now, assuming you allocate free memory using a best-fit strategy (that minimizes the size of the 'left-over' partition), describe what requests go in what partiions. Which algorithm makes the most efficient use of the memory?

  5. What is a relocation register? Describe briefly how an OS might be limited in its ability to manage memory use without a relocation register (or other memory management hardware).

  6. Consider a logical address space of 16 pages of 4096 bytes (words) each, mapped onto a physical memory of 64 frames.

    1. How many bits are there (minimum) in the logical address?
    2. How many bits are there (minimum) in the physical address?
    3. How many entries are there in the page table?
    4. How large, in bits, is the page table?

  7. Consider a paging system with the page table stored in memory.

    1. If the time to access physical memory is 110 nanoseconds, how long will be a paged memory reference?
    2. If we add associative registers (a TLB), and 90% of the memory references are in the associative registers, what is the the effective memory access time?
  8. What kind of fragmentation do we have with paging? Given N processes in memory, how much fragmentation do we have?

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